期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：8
DOI：10.15680/IJIRCCE.2015. 0308058
出版社：S&S Publications
摘要：The phase locked loop (PLL) has been widely used in wireless communication systems due to the highfrequency resolution and the short locking time. A phase-locked loop (PLL) is a closed-loop feedback control system,which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loopfilter, and the voltage controlled oscillator are the key parts of almost all PLLs. The phase-locked loops (PLLs) areprobably the most widely used synchronization technique in grid-connected applications. The Direct Digital Synthesis(DDS) is also an emerging and maturing signal generation technology. But another advanced technique in which, DDSsignal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoidingsome of the typical trade-offs in PLL. In particular, it is possible to achieve a very high-frequency resolution togetherwith fast settling and spectral purity. The proposed design consists in describing the mixed behaviour of this DDSbasedPLL architecture starting from the specifications of each building block. The HDL models of critical PLL blockshave been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noisesources has been efficiently introduced to study the system performance. The obtained results are composed withtransistor-level simulations to validate the effectiveness of the proposed models. The comparative study showed theperformances of different parameters. Finally, DDS- based PLL architecture is better than other architectures.
关键词：phase-locked loop; direct digital synthesiser; hardware description language; voltage controlled;oscillator; digital to analog converter; analog and mixed signal
