期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：8
DOI：10.15680/IJIRCCE.2015. 0308107
出版社：S&S Publications
摘要：High Performance Low Power 10T Full Adder (FA) is presented in this paper. FA is an essentialcomponent for the design of all types of processors viz. microprocessors and digital signal processors (DSP) etc.Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc.In most of these systems adder lies in the critical path that affects the overall speed of the system. So improving theperformance of the 1-bit FA circuit is a significant goal. The present work proposes an energy efficient FA circuit withfaster switching of output that reduces the serious problem of carry propagation from one adder to another adder.Result shows 10.56% improvement in Sum delay, 91.46% improvement in Carry delay over the other types of adderswith comparable performance of 8T and 9T FAs. The simulation has been carried out on Tanner EDA tool 14.1 at45nm technologies.
