期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：8
DOI：10.15680/IJIRCCE.2015. 0308108
出版社：S&S Publications
摘要：In the present work, Low Power Conditional Pulse Control Flip-Flop using Signal Feed through schemeis proposed. The proposed design removes the long discharging path problem with intermediate nodes using the pulsegeneration control (which facilitates a faster discharge operation). Transmission gate and three inverters are used tocontrol the clock circuit to reduce the power dissipation along the critical path. As a result, very low power dissipationoccurs when there is no switching. Tanner EDA tool 14.1 is used for the simulation purposes. All simulation results arebased on using CMOS 90-nm technology at 500MHz clock frequency. Its maximum power saving compared to PT-FFwith Pulse Enhancement Scheme FF design[1][2] is up to 26.84% and 14.72% than PT-FF with Pulse EnhancementScheme FF design [1].
关键词：Flip-Flop; Low power; Signal feed through scheme; Conditional pulse; Transmission gate circuit;Sequential circuits; Lower power dissipation
