期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310032
出版社：S&S Publications
摘要：Electronic circuits comprises of complex arithmetic units, o ne such field is DSP applications. Multiplier is the base of any arithmetic circuits. A system performance is generally determined b y the performance of the multiplier. Recent research activities in the field of arithmetic optimization combining operation which share date lead to significant performance improvement. The proposed optimized design of Add Multiply operator is based on the fusion of the adder and MB encoding unit into a single datapath block. For the design o f Fused Add Multiply (FAM) unit different recoding techniques are introduced(SMB1,SMB2,SMB3) for the odd and even bit width of input. These techniques are used to implement direct recoding of sum of two numbers in the Modified Boot h Form. Modified Booth Form are mainly used in multiplier, it reduce the number of partial products into half. By comparing the proposed recoding techniques with existing o ne , the proposed system yields considerable reduction in terms of area . The proposed FAM unit is coded in Verilog, simulated and synthesized using Xilinx tool
