期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310035
出版社：S&S Publications
摘要：The performance of the processors in DSP systems are mainly depend on the multipliers in it. This paper presents a power & area efficient multiprecision multiplier with a decreased delay. As multipliers are the key components in DSPs, microprocessors, FIR filters etc, it will adversely affect the performance of the system. Thus the main aim of the project is to increase the speed of the multiplier, for this some compression techniques were incorporated. This multiplier also enables parallel processing so th at it is possible to perform higher precision multiplications. The main focus of this paper is to increase the speed of the multipliers. The speed of a multiplier relies on generation of partial products. Here, it is suggested to use compressing techniques to improve the speed of multipliers. In addition to that scaling of supply voltage and frequency management are also done. This flexible multiplier combining variable precision processing, voltage and frequency management can be used efficiently to reduce circuit po wer consumption and delay. Simulatio n of results is done on ModelSim 6.3f and synthesis of power and area is done on Xilinx ISE Design 8.1.
关键词：DSP ; Multi precision; Parallel Processing; Compression
