期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310159
出版社：S&S Publications
摘要：The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with needof higher level of integration. In this project a low-power single-phase clock multiband flexible divider for Bluetooth,Zigbee, and Network standard‟s 802.15.4 and 802.11 a/b/g Wireless LAN frequency synthesizers is proposed based onpulse swallow topology and is implemented. The frequency synthesizer, usually implemented by a phase-locked loop(PLL), is one of the power-hungry blocks in the RF front-end and the first-stage frequency divider consumes a largeportion of power in a frequency synthesizer. The proposed pre-scalar based approach reduces the area and powersignificantly. The multiband divider consists of a proposed wideband multi modulus 32/33/47/48 pre-scalar and animproved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.41–2.483 GHz, 5.14–5.30 GHz, and 5.715–5.815 GHz with a resolution selectable from 1 to 25 MHz The proposed multiband flexibledivider is silicon verified and consumes power of 0.96 and 2.2 mw in 2.3-and 5-GHz bands, respectively, whenoperated at 1.8-V power supply. The proposed pre-scalar is achieved by without using any additional flip flops. It givesa solution to the low power PLL synthesizers for wide range of communication applications.
关键词：Pre-scalar; Dynamic logic; pluse- swallow topology; PLL synthesizer; Zigbee; Bluetooth
