期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310160
出版社：S&S Publications
摘要：This paper presents a delay measurement technique using signature analysis, and a scan design for theproposed delay measurement technique to detect small delay defects. The proposed measurement technique measuresthe delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator(VCG). Theproposed scan design realizes complete on-chip delay measurement in short measurement time using the proposedmeasurement technique and stores the test vectors using extra latches. The evaluation with Rohm 0.18- m processshows that the measurement time is 67.8% reduced compared with that of standard delay scan design on average. Thearea overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and thedifference of the area overhead between enhanced scan design and the proposed method is 7.4% on average.
关键词：Delay Measurement; Standard Scan Design;Signature Analysis;Variable Clock Generator(VGC)
