期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：11
DOI：10.15680/IJIRCCE.2015.0311138
出版社：S&S Publications
摘要：With the advent of new technology in the fields of VLSI and communication, there is also an evergrowing demand for high speed processing and low area design. It is also a well-known fact that the multiplier unitforms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need ofthe day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedicmath’s techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for additionhas also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplierintroduce in this paper, is almost two times faster than the popular methods of multiplication. Also we design a FFTusing compressor based multiplier. This all design and experiments were carried out on a Xilinx Spartan 3e series ofFPGA and the timing and area of the design, on the same have been calculated.
