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  • 标题:Review of 5 stage Pipelined Architecture of 8 Bit Pico Processor
  • 本地全文:下载
  • 作者:Shankar Kumar Mishra ; Dr. Nisha P Sarwade
  • 期刊名称:International Journal of Electronics, Communication and Soft Computing Science and Engineering
  • 印刷版ISSN:2277-9477
  • 出版年度:2014
  • 卷号:3
  • 期号:4
  • 出版社:IJECSCSE
  • 摘要:Proposed paper is the study of unpipelined architect ure of a 8 bit Pico Processor (pP) [3][4] and how its overall through put can be increased by implementing pipelining. Pico processor is an 8 bit processor which is similar to 8 bit microprocessors f or small embedded applications and it is intended for educational purpose .In the past un pipelined single cycle and multi cycle Pico Processor is implemented [3 ] .Its speed and overall through put can be increased by implementation of pipeline architecture [1] so that it can be used in small embedded applications like gaming processor
  • 关键词:Pico Processor; VHDL; RISC; Pipeline
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