期刊名称：International Journal of Electronics, Communication and Soft Computing Science and Engineering
印刷版ISSN：2277-9477
出版年度：2015
卷号：4
期号：Special 1
出版社：IJECSCSE
摘要：Everyday many users generate and interchange largeamount of information in various fields through Internet,telephone conversations etc. These and other examples ofapplications required a security, not only in the transport of suchinformation but also in its storage. Advanced EncryptionStandard (AES), a Federal Information Processin(FIPS), is an approved cryptographic algorithm that is used toprotect electronic data. As we share the data through wirelessnetwork it should provide data confidentiality, integrity andauthentication. AES has the advantage of being implementboth hardware and software. Hardware implementation of theAES has lot of advantage such has increased throughput andbetter security level. Hardware Implementation for 128 bit AES(Advanced Encryption Standard) encryption and Decryption hasbeen made using VHDL. The proposed algorithm for encryptionand decryption module will functionally verified using modelsim,will be synthesize using Quartus 2 using Altera FPGA platformand analyze the design for the power, Throughput & area
