期刊名称：International Journal of Computer Trends and Technology
电子版ISSN：2231-2803
出版年度：2016
卷号：32
期号：1
页码：8-13
DOI：10.14445/22312803/IJCTT-V32P102
出版社：Seventh Sense Research Group
摘要：A new architecture and simulation of an integer n frequency synthesizer using PLL for RF application has been illustrated in this paper. This design consists of low power phase frequency detector, low jitter charge pump, ring oscillator based VCO, passive loop filter and 8 bit frequency divider using 250nm technology. This presents the simplest way to design and simulate integer n frequency synthesizer and lock the PLL. The design and analysis of PLL is done on simulation EDA TANNER TOOL 13.0.The main benefit of using PLL technique in Frequency Synthesizer is that it can generate frequencies of 100 200MHz comparable to the accuracy of a crystal oscillator. This paper gives a brief introduction to the basics of Phase Locked loops.
关键词：Phase locked loop; Phase frequency detector; Charge pump; Loop filter; Voltage controlled oscillator; Frequency divider.
