期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：1
页码：18729
DOI：10.15680/IJIRSET.2015.0401052
出版社：S&S Publications
摘要：Multipliers are the basic building blocks of many VLSI computational units. The performance of suchVLSI circuits depends on the performance of multipliers. Hence designing a high performance multiplier is achallenging task for VLSI designers. Wallace tree multiplier or Wallace multiplier is the most popular multiplieramong the existing multipliers. Wallace multiplier is also known for its fast speed and low power consumption.Different techniques for designing a Wallace multiplier are available in the literature. In this paper, performancecomparison review of various Wallace multiplier architectures is included.
关键词：Wallace multiplier; Reduced complexity; Power Dissipation; Delay
