期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：3
页码：1148
DOI：10.15680/IJIRSET.2015.0403071
出版社：S&S Publications
摘要：In this paper, a new 128 bit QCA adder was presented. It achieved the speed performance higher than allthe existing adders. It decreases the number of QCA cells compared to previously testimony design. The proposedQCA adder design is based on new algorithm that requires only three majority gates and two inverters for the QCAaddition. The area necessity of the QCA adders is comparable cheap with the RCA and CFA established. The noveladder operated in the RCA fashion, but it could propagate a carry signal through a number of cascade MGs significallylower than conventional RCA adders. In addition, because of the adopted basic logic and layout approach, the numberof clock cycles required of completing the explanation was limited. As transistor decrease in size more and more ofthem can be accommodated in on its own die, thus increasing the chip computational capabilities. On the other hand,transistors cannot find much lesser than their existing size. The QCA approach represents one of the probable solutionsin overcome this physical limit, even though the design of logic modules in QCA is not forever uncomplicated.
