期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：6
页码：4031
DOI：10.15680/IJIRSET.2015.0406028
出版社：S&S Publications
摘要：As we know CMOS technology has many drawbacks like short channel effects, drain induced barrierlowering, hot carrier effect etc. So the designers are looking for new technology. CNT was developed in 1991 toovercome the drawbacks of CMOS. CNTFET has its structure similar to CMOS but the channel between source anddrain is replaced with carbon nano tubes. CNTFET works on the principle of ballistic transport. To improve itsperformance, diameter and threshold voltage are made variable parameters to make it an efficient device over CMOS.This variation is made possible with the help of chirality. In the present study, work has been done on full adder usingCNTFET and CMOS technology. Different parameters such as power dissipation, propagation delay and power delayproduct on 32nm model file are calculated for 0.9v, 1.0v and 1.1v power supply. Results of CNTFET and CMOS havebeen compared. All the work has been carried out on Tanner TOOL V14.1 and HSPICE Version B 2008.09. Circuitdesigning has been done on S-edit and simulation has been carried out using HSPICE. The waveform of full adder isshown using Avanwaves of HSPICE.
关键词：CMOS; CNTFET; chirality; full adder circuit; advantages of CNTFET; power dissipation; propagation;delay; power delay product; tanner tool v14.1; HSPICE version b 2008.09.
