期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：7
页码：5485
DOI：10.15680/IJIRSET.2015.0407088
出版社：S&S Publications
摘要：A high speed efficient TSPC flip-flop divide-by-16/17 dual modulus prescaler is proposed. The efficient(proposed) TSPC flip-flop with split path not only reduces the clock load and decrease power but also increases thespeed of operation. The speed of the precaler can improve in two aspects. First is by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is reduced by half a NOR gate’s delay. Second is by changing theconnection of TSPC D-Flip-flops, the minimum working period is reduced by half an inverter’s delay. The proposedcircuit is capable of operating up to 1.8GHz and is implemented in 5V, 0.18um CMOS technology. Simulations anddesigns are performed on Cadence Virtuoso and Spectre tools using UMC 0.18um technology.
