期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：7
页码：6276
DOI：10.15680/IJIRSET.2015.0407135
出版社：S&S Publications
摘要：Synchronous logic design is an important stream in designing the integrated circuits (IC). Flip-flops arethe basic building blocks in any synchronous design. A large amount of power is consumed by flip flops and latchesdue to redundant transitions and clocking system. In this paper, several flip-flops are analyzed and double edgetriggered clock pair shared flip flop using Multi-threshold voltage CMOS is proposed (DETCPSFF). The flip-flops areevaluated based on parameters such as delay, power. Simulation results shows the proposed design has less delay thanexisting designs, which claims that proposed design is suitable for high speed applications. The flip-flops are simulatedusing Mentor graphics in 130nm technology.
