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  • 标题:Design of a Low Power 10T SRAM Cell
  • 本地全文:下载
  • 作者:R. K. Sah ; M. kumar
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2015
  • 卷号:4
  • 期号:7
  • 页码:6334
  • DOI:10.15680/IJIRSET.2015.0407145
  • 出版社:S&S Publications
  • 摘要:SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadencevirtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delayproduct are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell,additional read circuitry is attached to avoid flipping of cell. The power dissipation, delay, and power delay product ofthe designed 10T SRAM cell in 180nm CMOS technology are found to be 22.08 x 10-9 W, 39.95 x 10-9 s and0.8820 x 10-15 Ws respectively.
  • 关键词:Power; Delay; Power Delay Product; 10T SRAM cell.
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