期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：8
页码：6936
DOI：10.15680/IJIRSET.2015.0408032
出版社：S&S Publications
摘要：Today, the entire device’s in electronics needs to be realized with low power and optimized Areaarchitectures because of power consumption and Area are of main consideration along with other performanceparameters. Low power consumption helps to reduce heat dissipation, increases battery life and also reliability.Arithmetic and Logic Unit (ALU) is one of the frequent and the most fundamental component in the processor design.In ALU, based on the observation, that if one functional unit is working other functional units remain idle, but they areconnected to clock and all units consuming significant amounts of power. By using clock gating technique, asignificant amount of power saving can be achieved at high frequencies. The clock gating reduces the power butincreases the overall area. Anti symmetric product coding (APC) and odd-multiple storage (OMS) are the techniquesthat used for area efficient design. This entire architecture captured using VHDL and has to be implemented on FPGAusing Xilinx tools.
