期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：11
页码：11112
DOI：10.15680/IJIRSET.2015.0411033
出版社：S&S Publications
摘要：Carry Select Adder (CSA) is one of many fast adderswhich can be used in data path applications. Wecan use new techniques to reduce the area, power and delay in the CSLA structure. This can be achieved by replacingone of the RCA block with any logic circuit which implements a logic to store the sum and carry for carry input 1 anduse it later. In our paper, a new design has been used by using a D-latch instead of using an RCA cascade structure forCin=0 or Cin=1. D-Latch is a single bit memory cell which gives same input as output with a delay and is controlled byan enable pin, it works only for enable high. If enable is low it stores the previous input, thus it serves the need ofstoring the sum and carry bits for RCA. In this way the area and speed can be improved. Hence we are designing 16-bitCSLA with parallel D-Latches which is the best adder design amongst all other previously existing adders.
