期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：12
页码：12121
DOI：10.15680/IJIRSET.2015.0412081
出版社：S&S Publications
摘要：This paper is devoted to the design of Quad core crypto processor for executing binary extension fieldinstructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform.Combination of two different field (prime field GF(P) and Binary extension field GF(2m)) instructions execution isanalyzed. Quad core will execute four instruction at a same time. The design is implemented in Spartan 3E , virtex4 andvirtex5. The performance results between them are compared. The implementation result shows the execution ofparallelism using dual field instructions.
关键词：Binary extension field; Cryptoprocessor; FPGA; Prime field
