期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：2
页码：2104
DOI：10.15680/IJIRSET.2016.0502060
出版社：S&S Publications
摘要：Power consumption is a major issue for integrated circuit design. Adders are basic building blocks forany arithmetic logic design and are majorly used in DSP processor, where computations are done with adders. In thispaper, we try to reduce the power consumption and area of the adder. In order to improve the performance of the digitalcomputer system one must improve the basic 1-bit full adder cell. In this paper we analysis the 1-bit full adder using 9Tfull adder design. We proposed the design of exact adder with reduced area and reduced complexity at the transistorlevel.
关键词：Power dissipation; CMOS; Approximate full adder; Mirror adder; Body Bias logic.
