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  • 标题:64-bit parallel CRC Generation for High Speed Applications
  • 本地全文:下载
  • 作者:P.Sushma ; N.Sushma ; V.Sowmya
  • 期刊名称:International Journal of Computer Applications and Information Technology
  • 印刷版ISSN:2278-7720
  • 出版年度:2014
  • 卷号:5
  • 期号:1
  • 页码:29-34
  • 出版社:Mahadev Educational Society
  • 摘要:CRC is playing a main role in the networking environment to detect the errors. . With challenging the speed of transmitting data, to synchronize with speed, it.s necessary to increase speed of CRC generation.Most electrical and computer engineers are familiar with the cyclic redundancy check (CRC). Many know that it.s used in commun ication protocols to detect bit errors, and that it.s essentially a remainder of the modulo -2long division operation. Some have had closer encounters with the CRC and know that it.s implemented as a linear feedback shift register (LFSR) using flip-flops and XOR gates. They likely used an online tool or an existing example to generate parallel CRC code for a design [1].
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