期刊名称：Vojnotehnicki glasnik / Military Technical Courier
印刷版ISSN：0042-8469
电子版ISSN：2217-4753
出版年度：2013
卷号：61
期号：4
页码：180-197
语种：
出版社：Ministry of defence of the Republic of Serbia: University of defence in Belgrade
摘要：The need for information security leads to big problems in the development of portable devices which have limited available memory space and power consumption. Also, if coprocessors for encryption are added to core processors, dimensions of such devices grow, they become inflexible and their price increases several times. It is, also, very well known that algorithms for data encryption are memory demanding and, because of a large number of operations that has to be executed during encryption and decryption, coprocessors often slow core processors. For one of cryptography standards, AES, the NIST has accepted Rijndael's block algorithm; the length of the input and output data stream is 128 bits, and the lengths of the cipher key can be 128, 192 and 256 bits. Due to the characteristics of low power consumption, a 32-bit architecture format, as well as fast execution of instructions, ARM processors implement the AES algorithm and do not burden the main processes in the system in which it is implemented. The ARM technology is protected as intellectual property, not as a processor design. As a result, many manufacturers have developed their own ARM-based products, so today over 2 billion chips are produced. This paper presents the possibilities for improving the performance of the AES algorithm using the latest version of the ARM processor.
