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  • 标题:Test Method for Encoder and Decoder Circuits used in Communication Networks
  • 本地全文:下载
  • 作者:Rita Jain* ; Mahendra Kumar Gupta
  • 期刊名称:International Journal of Electrical, Electronics and Computer Engineering
  • 电子版ISSN:2277-2626
  • 出版年度:2012
  • 卷号:1
  • 期号:1
  • 页码:9
  • 语种:English
  • 出版社:RESEARCH TREND
  • 摘要:ABSTRACT : Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub–circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built–In–Self–Test (BIST) technique has emerged as a cheap alternative.
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