期刊名称：International Journal of Electrical, Electronics and Computer Engineering
电子版ISSN：2277-2626
出版年度：2013
卷号：2
期号：2
页码：5
语种：English
出版社：RESEARCH TREND
摘要：ABSTRACT: A full adder is one of the most commonly used digital circuit component in any digital system design, over the years many improvements have been suggested to modify the architecture of a full adder. So far, the full adder of 10-T (transistors) architecture are considered as the most optimized design for performance and area. In this paper, 5 different types of 1 bit full adder namely 28T, 10T, 14T, Modified 14T and 12T adder is compared based on the basis of different parameters. The simulation has been carried out with properly defined simulation runs on a SPICE environment using a 0.25μm process. The results may be differing from those previously published, both for the more realistic simulations carried out and the more appropriate figure of merit used. The main objective is to find out Delay, Power and Power delay product (PDP) of different full adders’ scheme and carry out the comparison.
