期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：1
页码：739
DOI：10.15680/IJIRCCE.2016.0401160
出版社：S&S Publications
摘要：The next - generation video coding standard of High - Efficiency Video coding (HEVC) is particularly economical for coding high - resolution video like 8K - ultra - high - definition (UHD) video. Fractional motion estimation in HE VC presents a major challenge in clock latency and area cost because it consumes quite 40 take advantage of the overall encoding time and therefore results in high computational quality. With aims at supporting 8K - UHD video applications, an efficient inter polation filter VLSI architecture for HEVC is proposed during this paper. Firstly, a replacement interpolation filter algorithm supported the 8 - pixel interpolation unit is planned during this paper. It will save 19.7 business data processing time on the av erage with acceptable coding quality degradation. supported the planned algorithmic program, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeli ne interpolation filter engine, is given to scale back the implement hardware area and achieve high throughput
