期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：2
页码：1702
DOI：10.15680/IJIRCCE.2016.0402165
出版社：S&S Publications
摘要：In this paper, Authorshave presented the literature ondesigning of high speed, less area 64-bit ALU usingefficient techniques. The optimization of the proposed design will be done by using the different techniques. The parameters speed and area of the proposed design will be improved by using Carry Look Ahead Techniques. It also reducesthe circuit complexity. The ALU is a fundamental building block of central processing unit of a computer which is used in the simplest microprocessors for purpose of maintaining timers. Previously,manyefficient architecture have been introduced for the design of low complexity operation, but we have given the attention to the carry look ahead and reversible logic gate techniques. The proposed design of ALU will performs the mathematical, logical, and shifting operations like Addition, Subtraction, Multiplication, Increment,Decrement, Logical AND, Logical OR, Logical XOR etc.in the computer. In this paper, the efficient modules of ALU will be design using Xilinx software and simulation results will be verified on same platform using testbenches
