期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：2
页码：1809
DOI：10.15680/IJIRCCE.2016.0402181
出版社：S&S Publications
摘要：The design which utilizes different power modes will leads to reduction in energy consumption. In amulti-power-mode design, the range of the supply voltage becomes wide. Thus large clock skew may occur amongdifferent power domains in the system. Difference in arrival time of clock signal across the chip is called clock skew.Clock skew can be minimized by clock tree optimization which inserts Buffer chain to balance clock skew amongmodules. The novel architecture is composed of two serially connected sub-buffers which can operate at low and highvoltage level respectively. In the front sub-buffer, the low voltage level is used for coarse-grained reduction of clockskew. In the back sub-buffer, the high voltage level is used for fine-grained reduction of clock skew
关键词：Buffer; clock signal; Clock skew; Level Up Shifter; Sequential circuit
