期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：3
页码：2927
DOI：10.15680/IJIRCCE.2016.0403006
出版社：S&S Publications
摘要：Integrated circuits are tested using BIST technique which provides self-testability of the circuit and avoids the requirement of external testing equipment. This method achieves simultaneous testing of the circuits under online mode. The aim of proposed project is to design the active test set generator and comparator circuit and logic module with SRAM cells to store input test vectors and to reduce the switching activity with reduced testing time and Concurrent Test Latency(CTL). The proposed scheme is suitable for all types of IC'sand achievement of fault coverage is high
关键词：Built-In-Self Test; Active Test Set Generator and Comparator Circuit; Very Large Scale Integrated Circuits; Static Random Access Memory
