期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：3
页码：3577
DOI：10.15680/IJIRCCE.2016.0403154
出版社：S&S Publications
摘要：Multiplier is an important element in many signal processing systems. It is an area consuming and slowest element, its performance will determines the performance of a system itself. So that it is necessary to design an efficient multiplier in terms of satisfyingthe important parameters ofpower, area and speed.There are many researchers have been worked on the design of increasingly more efficient multipliers. They aim at achieving high speed and lower power consumption even while occupying reduced silicon area. This paper presents a new multiplier architecture that will increase the speed performance of the multiplierand also with reduced area.Simulation of 32 bit multiplier is carried out using modelsim SE PLUS 6.5band synthesis is done using Xilinx tool.
关键词：MUX; Wallace Multiplier; Full Adder; Half Adder
