期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2016
卷号：4
期号：4
页码：6376
DOI：10.15680/IJIRCCE.2016.0404012
出版社：S&S Publications
摘要：Nowadays multiplier plays an vital role in today's digital signal processing and other high performance system. With the help of multiplier nowadays various high speed, low power and compact system of VLSI implementation can be made. The conventional multiplier there is the reduction of delay, but the proposed multiplier will reduce the delay in each and every gate. By using the common Boolean logic, we can reduce the area,delay,power of the multiplier. And hence we can reduce the delay,area,power of each and every gates
关键词：Digital signal processing; common Boolean Logic; conventionalmultiplier
