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文章基本信息

  • 标题:CMOS Layout Design for Improved Latency Sequential Circuits
  • 本地全文:下载
  • 作者:Tiwari, S. K. ; Pathak, V.
  • 期刊名称:International Journal of Electronics Communication and Computer Engineering
  • 印刷版ISSN:2249-071X
  • 电子版ISSN:2278-4209
  • 出版年度:2016
  • 卷号:7
  • 期号:3
  • 页码:176-179
  • 出版社:IJECCE
  • 摘要:Microwind layout simulator is use to design thelatches and flip flops and to calculates the parametricanalysis such as power , switching delays, number oftransistors, data and clock frequencies etc. The CMOSlayouts are design and simulated for 8 bit asynchronouscounter, 16 state mealy sequential circuit, 16 slot first in firstout register for 8 bit data, and 4, 8 bit synchronize seriesconnected XOR base CRC generator. The average powerdissipation computed for these logic circuits are 22.29 μW,32.66 μW, 78.12 μW, 60.27 μW and 120μW.
  • 关键词:TG; FSM;FIFO; Synchronization; CRC
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