期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
卷号：3
期号：5
页码：12231
出版社：S&S Publications
摘要：This paper presents how po wer is reduced using voltage scaling method. By scaling the voltage down the power will be reduced but the low voltage increases the parametric failures like access, disturb and write. In this paper propose SRAM cell architecture with the application of low voltage for Lower ordered bits & nominal voltage for Higher ordered bits, because for multimedia applications like image, vidéo and audio has inherent error tolerance. The proposed SRAM cell architecture is constructed using 45nm technology(transistor size, with Gate Length is 45nm ).Simulations results is shown how power is reduced for proposed SRAM cell architecture in comparison with standard SRAM cell. Along with power reduction the proposed SRAM cell architecture is tested under process and temperature variations.
关键词：Voltage scaling; Low-po wer; SRAM cell; Process variation; Temperature variation; Multimedia ; applications
