期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
卷号：3
期号：5
页码：12792
出版社：S&S Publications
摘要：In today’s world, the complexity of the chip is increasing as more and more devices are being connectedon a single chip. Due to the high density of the chip, the power dissipation increases demanding better poweroptimization methods. One of the methods to achieve power optimization is by using reversible logic. It can be used inlow power CMOS designs, quantum computing, nanotechnology and optical computing.This paper presents an optimized sixteen-bit binary sequential counter based on reversible logic using Feynman, andFredkin gates. Optimization of the sequential circuit is achieved on the basis of total number of gates used in the circuitand total number of garbage outputs generated. Circuits have been designed using Cadence Virtuoso Schematic Editor.
