期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：NCET
页码：193
出版社：S&S Publications
摘要：This paper deals with Type-I Phase Locked Loop designed for an operating frequency of 1MHz,capture to lock frequency ratio as 0.63. Further the design is extended with low power techniques which aim atreducing the leakage power of the design. Two low power novel techniques called sleepy stack approach and dualmode logic are used. The existing design is modified with these two approaches and their combination for low powerdesigns. The designs are simulated in HSPICE synopsis tool and the waveforms are verified in Avanwaves tool. Theproposed design of PLL using both dual mode logic and sleepy stack approach reduces the power dissipation by nearly95% when compared to the existing design. Hence the low power PLL is best suited for practical applications as itdoesn’t deviate much from the specifications.
