期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：NCETAS
页码：114
出版社：S&S Publications
摘要：Now-a-days, the achievement of high speed, small circuitry area and low power consumption is beingconsidered by designers to fabricate modern digital circuits. Foe these full adders are one of the most importantcomponents for its wide use in subtraction, multiplication, filtering, DSP processors and Microprocessors. So, it is of agreat interest of the designers to design Carry Look Ahead (CLA) adder because of its high speed operation. In this paperwe have considered the power consumption and delay of a 4 bit CLA adder implemented in static CMOS and adiabatic2n2n2p logic.
