期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
卷号：3
期号：11
页码：17517
DOI：10.15680/IJIRSET.2014.0311061
出版社：S&S Publications
摘要：A Multiplier is one of the key hardware blocks in most digital and high performance systems such asFIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version oftree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latencyand power consumption. In conventional methods, 10T XNOR structure is used for Full adder design. In proposedmethod, 3T XNOR gate cell is used for Full adder design. Using this 3T XNOR technology, a 4:2 compressor has beendesigned and the design of a 5:2 compressor is proposed sing 3T XNOR technology which results in 8T Full adderdesign which reduces the transistor count when compared to conventional full adders. Hence the proposed compressorscan remarkably reduces power consumption. In this review article, various architectures and designs of arithmeticcircuits are discussed.
关键词：XNOR-XOR module; Full adder; Compressors; Multiplier
