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  • 标题:Implementation of a Low Power Carry Look Ahead Adder Using Adiabetic Logic
  • 本地全文:下载
  • 作者:Debika Chaudhuri ; Atanu Nag ; Sukanta Bose
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2014
  • 期号:NCETAS
  • 页码:119
  • 出版社:S&S Publications
  • 摘要:Now–a-days in digital circuit some important issues like high speed, high throughput, small silicon area,and low power consumption is being considered by designers. Full adders are important components in applicationssuch as subtraction, counting, multiplication, filtering, digital signal processors (DSP) architectures andmicroprocessors. So for designer it is a great interest to design Carry-look ahead adder because of its high speedoperation. In this paper power consumption and delay of a 4-bit carry look ahead adder, implemented in static CMOSand adiabetic logic (ECRL) is analyzed.
  • 关键词:Adiabatic Logic; Low power; CMOS; ECRL.
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