期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
期号：NCETAS
页码：124
出版社：S&S Publications
摘要：The aim of this paper is to evaluate the performance of One-bit full adder cell. Different Full Adder cellwith conventional static CMOS Adder is being compared. Each Cell showed different power consumption and Delay.Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuitperformance is power delay product (PDP).The driving capability of a full adder is very important, because, full addersare mostly used in cascade configuration, where the output of one provides the input for other. Here, we have given abrief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesserchip size. Starting from the most conventional 28 transistor full adder we have gradually studied full adders consistingof as less as 14 transistors (14 T), 16 transistors (16T), CMOS Transmission Gate (TG), Complementary Pass-transistorLogic (CPL), Gate Diffusion Input (GDI) and Static Energy Recovery Full Adder (SERF) to meet the requirements.
