期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
期号：ICIASET
页码：130
出版社：S&S Publications
摘要：To represent very large or small values, large range is required as the integer representation is no longerappropriate. These values can be represented using the IEEE 754 standard based floating point representation. Multiplyingfloating point numbers is a critical requirement for DSP applications involving large dynamic range. The paper describesthe implementation and design of IEEE 754 Pipelined Floating Point Multiplier based on Vedic Multiplication Technique.The inputs to the multiplier are provided in IEEE 754, 32 bit format. The Urdhva Triyakbhyam sutra is used for themultiplication of mantissa. The underflow and overflow cases are handled.
