期刊名称：International Journal of New Computer Architectures and their Applications
印刷版ISSN：2220-9085
出版年度：2011
卷号：1
期号：1
页码：112-122
出版社：Society of Digital Information and Wireless Communications
摘要：In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their flexibility and high performance. In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for full reconfigurable architecture. In fact, this algorithm optimizes the transfer of data required between design partitions. The proposed algorithm was tested on several examples on the Xilinx Virtex II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field
关键词：Temporal partitioning; data flow graph; full ; reconfigurable architectures; FPGA
