期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：7
页码：199-202
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the dsp design for digital FIR filter. Based on the design specification, careful choice of implementation method and tools can save a lot of time and work. There are toolboxes available to generate VHDL (Verilog) descriptions of the filters which reduce dramatically the time required to generate a solution. Time can be spent valuating different implementation alternatives. Proper choice of the computation algorithms can help the FPGA architecture to make it efficient in terms of speed and/or area.
关键词：Multiplier and accumulator; Booth ; algorithm; Booth Multiplier; Booth Wallace ; Multiplier; Adaptive Lattice Filter; Fir filter; ; Median filter; IIR filter.
