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  • 标题:Implementation Of Fully-Pipelined 16-Point DHT Architectures Using 8-Point And 4-Point DHTs for FPGA Realization
  • 本地全文:下载
  • 作者:J.Sridevi ; J.E.N.Abhilash ; J.Vasanta Kumar
  • 期刊名称:International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
  • 印刷版ISSN:2278-1323
  • 出版年度:2012
  • 卷号:1
  • 期号:9
  • 页码:256-260
  • 出版社:Shri Pannalal Research Institute of Technolgy
  • 摘要:Fully–pipelined simple modular structures arepresented in this project for efficient hardware realization ofDiscrete Hadamard transform (DHT).From the kernel matrixof HT three different pipelined modular designs are derivedfor transform length N=4.It is shown further that the HT oftransform length N=8 can be obtained from two 4-point HTmodules, and similarly, the HT of the transform length N=16can be obtained from four 4-point HT modules.Higher –length transforms can be obtained from these short lengthmodules as N-point transforms can be computed from 2Mnumber of M point HT-modules, where M=N1/2.The proposedarchitectures are coded in Verilog, simulated by Xilinx ISE toolfor validation and testing and may be synthesized thereafter tobe implemented in FPGA device, Spartan-3 and theperformance will be compared with the one of the presentstructures.
  • 关键词:Discrete Orthogonal Transforms (DOTs);Discrete Hadamard Transforms (DHTs); Best Achievable;Frequency (BAF); Field Programmable Gate Arrays (FPGA).
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