期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：2
页码：694-697
出版社：Shri Pannalal Research Institute of Technolgy
摘要：High speed and Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. Error-Tolerance is a novel method to enhance the effective yield of IC products.A large, extremely fast digital adder with some control block and carry free addition block is described. Without depending on the conventional design methods, a new method of addition is used.In this method the power dissipation due to carry propagation is greatly reduced unlike other conventional adders. Therefore, it is important to develop computational structures that fit well into the execution model of the processor and are optimized for the current technology. Optimization of the algorithms is performed globally across the critical path of its implementation.In this methodology, 64 bit design of Error Tolerant Adder is implemented and is verified from simulation outputs using CADENCE ENCOUNTER COMPILER. The results show that proposed 64 bit architecture fair better in terms of power and delay compared to previous approaches.
关键词：Power Delay Product(PDP);Multiply and ; Accumulate(MAC);Least Significant Bit(LSB);Most Significant ; Bit(MSB); Digital Signal Processing (DSP).
