期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：3
页码：1036-1040
出版社：Shri Pannalal Research Institute of Technolgy
摘要：In this paper, a new MAC architecture is developed for high speed performance. The performance can be improved by developing a new carry save adder which is designed by combining multiplication with accumulation. The overall performance will be improved because of merging the accumulator, which has largest delay, into CSA. The CSA tree uses modified Booth algorithm(MBA) which provides the high accuracy instead of using radix 2 modified booth algorithm in present technique. Least significant bits are generated in advance to reduce the number of inputs to the final adder by propogating carries to the least significant bits by CSA. Instead of the final adder output, the intermediate results, sum and carry, are accumulated. The MAC architecture is synthesized with 180nm standard CMOS library using cadence SOC encounter.
关键词：Carry save adder; digital signal processing; modified booth algorithm; multiplier-and-accumulator
