期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：4
页码：1614-1618
出版社：Shri Pannalal Research Institute of Technolgy
摘要：In this paper Two Hybrid digital circuit design techniques are produced as Hybrid Multi- Threshold CMOS complete stack technique and Hybrid Multi-Threshold CMOS partial stack technique for reducing the leakage power dissipation in mode transistion.Tri-modal switch are performance depends on these two techniques reduce the leakage power dissipation. These technique are implemented in the CADENCE virtuoso tool to find the leakage power dissipation and propagation delay. This proposed Hybrid techniques are proved better leakage power reduction than the MTCMOS techniques.
