期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：7
页码：2230-2231
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The digital circuit layout problem is a constrained optimization problem in the combinatorial sense. It is accomplished in several stages such as partitioning, floorplanning, placement and routing with each step being a constrained optimization problem. Partitioning is one of the first steps in VLSI circuit design. The technique is applied recursively until the complexity in each subdesign is reduced to the extent that it can be handled efficiently by existing tools. This technique is of great importance since it directly affects the rest of the steps in the process. The paper presents three encoding techniques for representation of circuit in the form graph for solving the circuit partitioning problem in context with Digital circuit Layout.
