期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：7
页码：2357-2362
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed. Row- bypassing multiplier, column-bypassing multiplier and bruan multipliers are implemented in conventional method and GDI technique. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). the experimental results show that our proposed low-cost low power multiplier saves hardware cost and reduces the power dissipation.
关键词：Row bypassing multiplier; Column bypassing ; multiplier; GDI ; and power dissipation
