期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：11
页码：2836-2840
出版社：Shri Pannalal Research Institute of Technolgy
摘要：COMPARATOR is the basic module in digital system. It is widely used in communication and calculation areas. Traditional comparator circuit is based on truth table leads to high power consumption, low speed and increased area. The main objective of this paper is to provide new low power, area solution for very large scale integration (VLSI) designers. At circuit level, STATIC CMOS logic style can give better results over others when we design efficiently. In this project the proposed comparator has been designed by using STATIC CMOS 180nm TECHNOLOGY. Layout for comparator has been implemented by using tanner tool.
