期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：2
页码：534-539
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Network on-chip is a novel designing communication protocol. It creates a communication between the on-chip cores. It has been proposed as one of the interconnect solutions for future systems-on-chip (SoCs). This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method for a Network-on Chip (NoC). The proposed architecture contains a special scan cell and an Embedded Test Core (ETC) as its test source. The ETC performs a static flow control and a centric average power consumption control during the proposed test mechanism. This shows the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth, high area and energy efficiency. The proposed BIST methodology enables a fast go/no-go BIST, with minor extra area in the NoC itself. Chip design is becoming increasingly communication-bound rather than computation-bound. In this paper the test scheduling problem is also addressed for such NoC-based SoCs. We assume a hybrid BIST approach, where test sets of individual cores are composed of pseudorandom and deterministic test sequences and, contrary to many other scheduling approaches, not treated as black boxes. This work also presents two more technique called N-detect test relaxation and hybrid algorithm to improve the performance of the system.
